1. Technical Field of the Invention
The present invention generally relates to a method for fabricating a dielectric material that has an ultralow dielectric constant (or ultralow-k) associated therewith and an electronic device containing such a dielectric material. More particularly, the present invention relates to a method for fabricating a thermally stable ultralow-k film for use as an intralevel or interlevel dielectric in an ultra-large-scale integration (xe2x80x9cULSIxe2x80x9d) back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring structure and an electronic structure formed by such method.
2. Description of the Prior Art
The continuous shrinking in dimensions of electronic devices utilized in ULSI circuits in recent years has resulted in increasing the resistance of the BEOL metallization as well as increasing the capacitance of the intralayer and interlayer dielectric. This combined effect increases signal delays in ULSI electronic devices. In order to improve the switching performance of future ULSI circuits, low dielectric constant (k) insulators and particularly those with k significantly lower than silicon oxide are needed to reduce the capacitances. Dielectric materials (i.e., dielectrics) that have low-k values have been commercially available. For instance, one of such materials is polytetrafluoroethylene (xe2x80x9cPTFExe2x80x9d), which has a k value of 2.0. However, these dielectric materials are not thermally stable when exposed to temperatures above 300xcx9c350xc2x0 C. Integration of these dielectrics in ULSI chips requires a thermal stability of at least 400xc2x0 C. Consequently, these dielectrics are rendered useless during integration.
The low-k materials that have been considered for applications in ULSI devices include polymers containing Si, C, O, such as methylsiloxane, methylsilsesquioxanes, and other organic and inorganic polymers. For instance, a paper (N. Hacker et al. xe2x80x9cProperties of new low dielectric constant spin-on silicon oxide based dielectrics.xe2x80x9d Mat. Res. Soc. Symp. Proc. 476 (1997): 25) described materials that appear to satisfy the thermal stability requirement, even though some of these materials propagate cracks easily when reaching thicknesses needed for integration in the interconnect structure when films are prepared by a spin-on technique. Furthermore, the precursor materials are high cost and prohibitive for use in mass production. In contrast to this, most of the fabrication steps of very-large-scale-integration (xe2x80x9cVLSIxe2x80x9d) and ULSI chips are carried out by plasma enhanced chemical or physical vapor deposition techniques. The ability to fabricate a low-k material by a plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) technique using readily available processing equipment will simplify the material""s integration in the manufacturing process, reduce manufacturing cost, and create less hazardous waste. U.S. Pat. Nos. 6,147,009 and 6,497,963 assigned to the common assignee of the present invention and incorporated herein by reference in their entirety, described an ultralow dielectric constant material, consisting of Si, C, O and H atoms, having a dielectric constant not more than 3.6, and exhibiting very low crack propagation velocities.
U.S. Pat. Nos. 6,312,793, 6,479,100 and 6,312,797 assigned to the common assignee of the present invention and incorporated herein by reference in their entirety, described a dual-phase material, consisting of a matrix composed of Si, C, O, and H atoms, a phase composed of mainly C and H atoms, and having a dielectric constant of not more than 3.2. It should be noted that continued reduction of the dielectric constant of such materials will further improve the performance of electronic devices incorporating such dielectrics.
In view of the foregoing, there is a continued need for developing a dielectric material that has a dielectric constant of not more than about 2.8 and inhibits cracking.
It is therefore an object of the present invention to provide a method for fabricating an ultralow dielectric constant material having a dielectric constant of not more than about 2.8. More preferably, the dielectric constant for the ultralow-k material is in a range of about 1.5 to about 2.5, and most preferably, the dielectric constant is in a range of about 2.0 to about 2.25. It should be noted that all dielectric constants are relative to a vacuum unless otherwise specified.
It is another object of the present invention to provide a method for fabricating an ultralow dielectric constant material comprising Si, C, O and H atoms from a mixture of at least two precursors, wherein one precursor is selected from molecules with ring structures comprising SiCOH components and the second precursor is an organic molecule selected from the group consisting of molecules with ring structures.
It is a further object of the present invention to provide a method for fabricating an ultralow dielectric constant film in a parallel plate plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) reactor.
It is yet a further object of the present invention to provide an improved method for fabricating an ultralow dielectric constant material by depositing a film on a substrate in the presence of inert gas, such as He or Ar, thereby improving uniformity of the film deposited and stabilizing the plasma within the PECVD reactor.
It is another object of the present invention to provide a method for fabricating an ultralow dielectric constant material for use in electronic structures as an intralevel or interlevel dielectric in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) interconnect structure.
It is yet another object of the present invention to provide a thermally stable ultralow dielectric constant material that has low internal stresses and a dielectric constant of not higher than about 2.8. More preferably, the dielectric constant for the ultralow-k material is in a range of about 1.5 to about 2.5 and, most preferably, the dielectric constant is in a range of about 2.0 to about 2.25.
It is still another object of the present invention to provide an electronic structure incorporating layers of insulating materials as intralevel or interlevel dielectrics in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring structure in which at least two of the layers of insulating materials comprise an ultralow dielectric constant material of the present invention.
It is yet a further object of the present invention to provide an electronic structure, which has layers of the inventive ultralow dielectric constant material as intralevel or interlevel dielectrics in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring structure and which further contains at least one dielectric cap layer as a reactive ion etch (xe2x80x9cRIExe2x80x9d) mask polish stop or a diffusion barrier.
In accordance with the present invention, there is provided a method for fabricating a thermally stable dielectric material that has a matrix comprising Si, C, O, and H atoms and an atomic level nanoporosity. In a preferred embodiment, the dielectric material has a matrix that consists essentially of Si, C, O, and H. The present invention further provides a method for fabricating the dielectric material by reacting a first precursor gas comprising atoms of Si, C, O, and H and at least a second precursor gas comprising atoms of C, H, and optionally O, F and N in a plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) reactor. The present invention further provides an electronic structure (i.e., substrate) that has layers of insulating materials as intralevel or interlevel dielectrics used in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring structure, wherein the insulating material can be the ultralow-k film of present invention.
In a preferred embodiment, there is provided a method for fabricating a thermally stable ultralow dielectric constant (ultralow-k) film comprising the steps of: providing a plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) reactor; positioning an electronic structure (i.e., substrate) in the reactor; flowing a first precursor gas comprising atoms of Si, C, O, and H into the reactor; flowing a second precursor gas mixture comprising atoms of C, H and optionally O, F and N into the reactor; and depositing an ultralow-k film on the substrate. Preferably, the first precursor is selected from molecules with ring structures comprising SiCOH components such as 1,3,5,7-tetramethylcyclotetrasiloxane (xe2x80x9cTMCTSxe2x80x9d or xe2x80x9cC4H16O4Si4xe2x80x9d). The second precursor may be an organic molecule selected from the group consisting of molecules with ring structures, preferably with more than one ring present in the molecule. Especially useful, are species containing fused rings, at least one of which contains a heteroatom, preferentially oxygen. Of these species, the most suitable are those that include a ring of a size that imparts significant ring strain, namely rings of 3 or 4 atoms and/or 7 or more atoms. Particularly attractive, are members of a class of compounds known as oxabicyclics, such as cyclopentene oxide (xe2x80x9cCPOxe2x80x9d or xe2x80x9cC5H8Oxe2x80x9d).
Optionally, the deposited film of the present invention can be heat treated at a temperature of not less than about 300xc2x0 C. for a time period of at least about 0.25 hour. The method may further comprise the step of providing a parallel plate reactor, which has an area of a substrate chuck between about 300 cm2 and about 800 cm2, and a gap between the substrate and a top electrode between about 1 cm and about 10 cm. A high frequency RF power is applied to one of the electrodes at a frequency between about 12 MHZ and about 15 MHZ. Optionally, an additional RF power can be applied to the same or different electrode. The heat-treating step may further be conducted at a temperature not higher than about 300xc2x0 C. for a first time period and then at a temperature not lower than about 380xc2x0 C. for a second time period, the second time period being longer than the first time period. The second time period may be at least about 10 times the first time period.
The deposition step for the ultralow dielectric constant film of the present invention may further comprise the steps of: setting the substrate temperature at between about 25xc2x0 C. and about 400xc2x0 C.; setting the high frequency RF power density at between about 0.05 W/cm2 and about 4.0 W/cm2, preferably from greater than 0.5 W/cm2 to about 4.0 W/cm2, and even more preferably from greater than 2.0 W/cm2 to about 4.0 W/cm2; setting the first precursor flow rate at between about 5 sccm and about 1000 sccm; setting the flow rate of the second precursor between about 5 sccm and about 50,000 sccm, preferably from greater than 1000 sccm to about 50,000 sccm; setting the reactor pressure at a pressure between about 50 mTorr and about 5000 mTorr; and setting the high frequency power between about 15 W and about 500 W. Optionally, another RF power may be added to the plasma between about 10 W and about 300 W. When the area of the substrate chuck is changed by a factor of X, the RF power applied to the substrate chuck is also changed by a factor of X.
In another preferred embodiment, there is provided a method for fabricating an ultralow-k film comprising the steps of: providing a parallel plate type chemical vapor deposition reactor that has plasma enhancement; positioning a pre-processed wafer on a substrate chuck which has an area of between about 300 cm2 and about 800 cm2 and maintaining a gap between the wafer and a top electrode between about 1 cm and about 10 cm; flowing a first precursor gas comprising cyclic siloxane molecules into the reactor; flowing at least a second precursor gas comprising organic molecules with ring structures including C, H and O atoms; and depositing an ultralow-k film on the wafer. The process may further comprise the step of heat-treating the film after the deposition step at a temperature of not less than about 300xc2x0 C. for at least about 0.25 hour. The process may further comprise the step of applying a RF power to the wafer. The heat-treating step may further be conducted at a temperature of not higher than about 300xc2x0 C. for a first time period and then at a temperature not lower than about 380xc2x0 C. for a second time period, the second time period being longer than the first time period. The second time period may be at least about 10 times the first time period.
The cyclic siloxane precursor utilized can be tetramethylcyclotetrasiloxane (xe2x80x9cTMCTSxe2x80x9d) and the organic precursor can be cyclopentene oxide (xe2x80x9cCPOxe2x80x9d). The deposition step for the ultralow-k film may further comprise the steps of: setting the wafer temperature at between about 25xc2x0 C. and about 400xc2x0 C.; setting a RF power density at between about 0.05 W/cm2 and about 4.0 W/cm2, preferably greater than 2.0 W/cm2 to about 4.0 W/cm2; setting the flow rate of the cyclic siloxane between about 5 sccm and about 1000 sccm; setting the flow rate of the organic precursor between about 5 sccm and about 50,000 sccm, preferably greater than 1000 sccm to about 50,000 sccm; and setting the pressure in the reactor at between about 50 mTorr and about 5000 mTorr and depositing a dielectric film on the wafer in the presence of an inert gas such as He, Ar, Ne, Kr or Xe. Additionally, the deposition step may further comprise setting a flow ratio of cyclopentene oxide to tetramethylcyclotetrasiloxane to between about 1 and about 80, preferably between 10 and 60. The area of the substrate chuck can be changed by a factor X, which leads to a change in RF power by the same factor X.
In still another preferred embodiment, there is provided a method for fabricating a thermally stable ultralow-k dielectric film comprising the steps of: providing a plasma enhanced chemical vapor deposition reactor of a parallel plate type; positioning a wafer on a substrate chuck that has an area between about 300 cm2 and about 800 cm2 and maintaining a gap between the wafer and a top electrode between about 1 cm and about 10 cm; flowing a precursor gas mixture of a cyclic siloxane with a cyclic organic molecule into the reactor over the wafer, which is kept at a temperature between about 60xc2x0 C. and about 200xc2x0 C., at a total flow rate between about 25 sccm and about 5000 sccm, preferably greater than 500 sccm to about 5000 sccm, while keeping the reactor pressure at between about 100 mTorr and about 5000 mTorr; depositing a dielectric film on the wafer under a RF power density between about 0.25 W/cm2 and about 4 W/cm2, preferably greater than 0.8 W/cm2 to about 4 W/cm2; and annealing the ultralow-k film at a temperature of not less than about 300xc2x0 C. for at least about 0.25 hour. The inventive method may further comprise the step of annealing the film at a temperature of not higher than about 300xc2x0 C. for a first time period and then at a temperature not lower than about 380xc2x0 C. for a second time period, wherein the second time period is longer than the first time period. The second time period may be set at least about 10 times the first time period. The cyclic siloxane precursor can be tetramethylcyclotetrasiloxane (xe2x80x9cTMCTSxe2x80x9d) and the cyclic organic precursor can be cyclopentene oxide (xe2x80x9cCPOxe2x80x9d).
The present invention is further directed to an electronic structure which has layers of insulating materials as intralevel or interlevel dielectrics in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) interconnect structure which includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material of the inventive ultralow-k dielectric, the ultralow-k dielectric comprising Si, C, O and H, and a multiplicity of nanometer-sized pores, and having a dielectric constant of not more than about 2.8, the second layer of insulating material being in intimate contact with the first layer of insulating material, the first region of conductor being in electrical communication with the first region of metal, and a second region of conductor being in electrical communication with the first region of conductor and being embedded in a third layer of insulating material comprising the inventive ultralow-k dielectric, the third layer of insulating material being in intimate contact with the second layer of insulating material. The electronic structure may further comprise a dielectric cap layer situated in-between the second layer of insulating material and the third layer of insulating material. The electronic structure may further comprise a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material, and a second dielectric cap layer on top of the third layer of insulating material.
The dielectric cap material can be selected from silicon oxide, silicon nitride, silicon oxynitride, a refractory metal silicon nitride (wherein the refractory metal is selected from the group consisting of Ta, Zr, Hf and W), silicon carbide, carbon doped oxide or SiCOH and their hydrogenated compounds. The first and the second dielectric cap layers may be selected from the same group of dielectric materials. The first layer of insulating material may be silicon oxide or silicon nitride or doped varieties of these materials, such as phosphorus silicate glass (xe2x80x9cPSGxe2x80x9d) or boron phosphorus silicate glass (xe2x80x9cBPSGxe2x80x9d). The electronic structure may further include a diffusion barrier layer of a dielectric material deposited on at least one of the second and third layers of insulating material. The electronic structure may further comprise a dielectric on top of the second layer of insulating material, which acts as a reactive ion etch (xe2x80x9cRIExe2x80x9d) hard mask and polish stop layer and a dielectric diffusion barrier layer on top of the dielectric RIE hard mask and polish stop layer. The electronic structure may further comprise a first dielectric RIE hard mask/polish-stop layer on top of the second layer of insulating material, a first dielectric RIE hard mask/diffusion barrier layer on top of the first dielectric polish-stop layer, a second dielectric RIE hard mask/polish-stop layer on top of the third layer of insulating material, and a second dielectric diffusion barrier layer on top of the second dielectric polish-stop layer. The electronic structure may further comprise a dielectric cap layer of same materials as mentioned above, between an interlevel dielectric of ultralow-k dielectric and an intralevel dielectric of ultralow-k dielectric.